Alliance is a complete set of free CAD tools and cell libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, and automatic place and route tools. A complete set of portable CMOS libraries is provided. It covers a wide range of the standard design flow (from VHDL up to layout). Alliance is the result of a twelve year effort spent at ASIM department of LIP6 laboratory of the Pierre et Marie Curie University (Paris VI, France). It includes;

Alliance has been used for research projects such as the 875.000 transistors StaCS superscalar microprocessor and 400.000 transistors IEEE Gigabit HSL Router. It's enclosed on Fedora Electronic Laboratory project, Fedora Electronic Lab live DVD.
 

           

The Electric (a trademark of Static Free Software, a division of RuLabinsky Enterprises, Incorporated) VLSI Design System is an open-source Electronic Design Automation (EDA) system that can handle many forms of circuit design, including:

is written in the Java programming language and is distributed as a single ".jar" file to launch with command java -jar name_file.jar. Electric has many synthesis tools, including routing, compaction, silicon compilation, PLA generation, and compensation. There are various plugins; Electric plug-ins are additional pieces of code that can be downloaded separately (from here) to enhance the system's functionality. Electric reads and writes libraries of circuitry in its own binary format. For portability between computers, it is also able to read and write a textual format of its database. However, for maximum compatibility with other EDA systems, Electric supports a number of popular interchange and manufacturing formats: CIF (Caltech Intermediate Format - I/O), GDS II (Calma GDS interchange format - I/O), EDIF (Electronic Design Interchange Format - I/O), SUE (Schematic User Environment - only Input), DXF (AutoCAD mechanical format - I/O), VHDL (Hardware description language - I/O), Verilog (Hardware description language - only Output), CDL (Cadence's circuit description language - only Output), EAGLE (Schematic capture interface - only Output), ECAD (Schematic capture interface - only Output), HPGL (Plotting language - only Output), Postscript (Plotting language - only Output).

           

Glade (Gds, Lef And Def Editor) is a freeware IC layout editor capable of reading GDS2, OASIS, LEF and DEF. It's distributed under freeware license. Some features are;

• Fast, hardware accelerated OpenGL graphics;
• Import/Export GDS2, OASIS, DXF, LEF, DEF and Verilog;
• Import Cadence display.drf and techfiles directly;
• Edit and display hierarchy from 0 to an unlimited number of levels;
• Create instance, label, rectangle, path, polygon, via, pin commands with interactive display during enter;
• Layer select window for setting layer visibility/selectability, current layer, choosing layer colour and transparency, fill pattern, line style/width and setting layer names;
• ...and many others!

           

LayoutEditor is a program to design and edit layouts for MEMS/IS fabrication. It has sophisticated functions like all angles, font generator, macros, boolean operations, design rule checker, netlist driven layout and LVS. The Calma GDSII file format is used as the primary file format. Also OASIS (Open Artwork System Interchange Standard), DXF and CIF (Caltech Intermediate Form) are full supported. Gerber (e.g. Gerbv and KiCAD), Alliance, Lasi (Layout System for Induvials) file can be imported, but an export to the Lasi file format is not possible. Designing these layouts require a high precision. So a sufficient resolution and a possibility of a high scaling is required. The resolution of the LayoutEditor can be set in a wide range and is normally set to 1 nano meter. This is enough for IC/MEMS which extend usually less than 0.1 meters. The productions of MEMS/IC is done in many layers. For each of these physical layer a belonging layer had to exist in the drawing. Additional logical layers are required for describing/naming purpose. So a lot of layers are needed. By default the LayoutEditor is limited to 128 layers. But it can easily be adjusted, if more layers are required. Designs often contain a plenty of repeating structures. Essential for managing these designs is therefor a hierarchical design. This means, that the complete repeating structure only exists once in a single cell. These cell is then referred multiple times in the main drawing. Site juspertor UG was founded in 2009 to provide an optimal support for users. LayoutEditor is published under the General Public License a version 2. If you are not familiar with this license, please read it carefully. Nevertheless some additional features are incompatible to the GPL. These functions are only available as a Full Version without the source code. The commercial use of the Full Version is exclusive for supporters of this project. All compiled (binary) versions of the LayoutEditor are Full Version. The LayoutEditor is crossplatform compatible and runs on GNU/Linux and much more platforms. For more informations click here.