HDLmaker (from Polybus System Corp) generates hierarchical Verilog and VHDL code, PCB netlists, simulation and synthesis scripts/projects/make files, and schematics. HDLmaker projects are based on two types of files; .top files which describe the hierarchy and connectivity of the design, and .pin files which describe the pins on Verilog modules, VHDL entities and chips. In it's simplest form HDLmaker can be used to tie together a simple list of components, however HDLmaker also incorporates a C like language which can be used to generate complicated designs and even to floor plan a Xilinx FPGA. It can translate Verilog/VHDL and HDLmaker projects into HTML with hyper links from all source files (hyperlinking between the modules) to generated files and from all component instances to the component's module. Verilog and VHDL HTMLized are also syntax colored. It can also translate PADS PCB netlists into Verilog and VHDL and can do some simple VHDL to Verilog translations. HDLMaker synplifies the development of complex FPGAs and ASICs, and has extensive support for most Xilinx FPGAs (e.g. Virtex4, Virtex2P, Virtex2, VirtexE, Virtex, Spartan3, Spartan2, 4000E, 4000EX, 4000XL, 5200, 9500 and so on). HDLmaker is available under the BSD license.