JTAG (IEEE 1149.1) is a serial interface for testing devices with integrated circuits. The problem that the JTAG interface was designed to solve is checking if connections between ICs are OK. Therefore you can set and check in- and outputs of ICs. In order to save pins and logic a very simple serial design was invented.

• One pin serial input;
• One pin serial output;
• One pin clock;
• One pin control.

The control pin (together with clock) allows to switch device states. A state machine inside each chip can be controlled, e.g. to reset the device. This control machine also allows to have two internal shift registers in each device (although we only have on in- and one output-pin). The registers are called instruction register (IR) and data register (DR). UrJTAG aims to create an enhanced, modern tool for communicating over JTAG with flash chips, CPUs, and many more. It is a descendant of the popular openwince JTAG tools with a lot of additional features and enhancements. The current UrJTAG tool allows you to set the IR and set and get the DR. Some supported adapters/cables, parts (chips) are;

• Arcom JTAG Cable;
• Altera USB-Blaster and compatible;
• Xilinx DLC5 JTAG Parallel Cable III;
• ETC EA253 JTAG Cable;
• Lattice Parallel Port JTAG Cable;
• ...and many others!

• Altera EP1C20F400;
• Atmel ATmega128 (partial support);
• Broadcom BCM1250;
• Hitachi HD64465;
• Intel SA1110;
• Lattice LC4032V;
• Motorola MPC8245;
• Toshiba TX4925/TX4926;
• Xilinx XCR3256XL-FT256;
• ...and many others!

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